Nowadays in very-large-scale-integrated-circuits (VLSIC) a continuously increased amount of technical functions is realized on a continuously decreased size. For housing such a highly integrated circuit the Ball-Grid-Array-(BGA)-Technology has been developed. In BGA technology the pins are arranged comparatively compact as solder balls in a grid of columns and rows on the lower surface of the housing for a Surface-Mounted-Device (SMD) assembling. In a reflow solder process in a soldering furnace the solder balls are fused and are combined with contact pads on a Printed-Circuit-Board (PCB).
With increasing integration in the VLSI circuits the diameter of the contact balls has decreased from 600 Micrometer a few years ago to 200 Micrometer nowadays, whereas the distance between the contact balls in the grid simultaneously has diminished from 1000 Micrometers a few years ago to 500 Micrometer today and will reach 400 Micrometer in nearest future. Consequently, the width of a signal line between two contact balls decreases from 75 Micrometer a few years ago to 50 Micrometer today and the space distance between a signal line and a contact pad decreases from 100 Micrometer a few years ago to 50 Micrometer today. Future ambition yields to lead at least two signal lines between two contact pads will result in a fewer amount of substrate layers in the printed circuit board.
A further reduction of the width for the signal line and for the space distance between a signal line and a contact pad is difficult to achieve, because the current running over the signal line requires a specific minimum signal line width and a specific space distance to the next contact ball for radio frequency reason.
Typically, for connecting a pin of the VLSI circuit with multiple electronic components on the printed circuit board via a corresponding signal line a via hole is realized connecting the contact pad on the upper surface with another contact pad on the lower surface of the substrate layer in case of a single-layered PCB or with contact pads on an upper and/or a lower surface of each substrate layer in case of a multi-layered PCB.
US 2014/0123489 A1 shows a via hole with a through connection between signal lines on the surfaces on substrate layers in a multi-layered PCB.
The connection between each contact pad in the via-hole is realized by coating the circumference of the via-hole with a sleeve-sized conductive layer. The coating thickness of this sleeve-sized conductive layer is optimized to approximately 25 Micrometer nowadays enabling both a sufficient current leading characteristic and a minimized diameter for the via-hole and consequently for the contact pad.
Thermal stress during reflow soldering at approximately 250° Celsius leads to a gas emission of residual moisture in the substrate layer of the printed circuit board. This disadvantageously results in a burst of the conductive layer preferably at the corner between the sleeve-sized conductive layer on the circumference of the via-hole and the conductive layer on the upper or lower surface of the printed circuit board if the sleeve-sized conductive layer of the via-hole has a coating thickness of approximately 25 Micrometer.
One object of the invention among others is to provide a printed circuit board with at least one substrate layer containing at least one via hole which overcomes the disadvantageous burst of the conductive layer at the corner between the via hole and the upper resp. lower surface and to provide a corresponding production method for such a printed circuit board.